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10-BIT, 50MSPS, 50mW A/D CONVERTER
NOT FOR NEW DESIGN
DESCRIPTION
N
10-bit A/D converter in deep submicron CMOS technology Single supply voltage: 2.5V Input range: 2Vpp differential 50Msps sampling frequency Ultra low power consumption: 50mW @ 50Msps ENOB=9.6 @ 40Msps, Fin=24MHz SFDR typically up to 72dB @ 50Msps, Fin=5MHz Built-in reference voltage with external bias capability Pinout compatibility with TSA0801, TSA1001 and TSA1201
ORDER CODE
Part Number TSA1002CF TSA1002IF
E
Temperature Range 0 C to +70 C 0 C to +70 C
S
Package TQFP48 TQFP48 TQFP48 TQFP48 Conditioning Tray Tape & Reel Tray Tape & Reel Marking SA1002C SA1002C SA1002I SA1002I Evaluation board
47 46 45 44 43
TSA1002CFT TSA1002IFT
W
EVAL1002/AA
D
-40 C to +85 C -40 C to +85 C
IG
VCCB GNDB OEB
E
PIN CONNECTIONS (top view)
bs O
The TSA1002 is a 10-bit, 50Msps sampling frequency Analog to Digital converter using a CMOS technology combining high performances and very low power consumption. The TSA1002 is based on a pipeline structure and digital error correction to provide excellent static linearity and guarantee 9.6 effective bits at Fs=40Msps, and Fin=24MHz. A voltage reference is integrated in the circuit to simplify the design and minimize external components. It is nevertheless possible to use the circuit with an external reference. Especially designed for high speed, low power applications, the TSA1002 only dissipates 50mW at 50Msps. A tri-state capability, available on the output buffers, enables to address several slave ADCs by a unique master. The output data can be coded into two different formats. A Data Ready signal is raised as the data is valid on the output and can be used for synchronization purposes. The TSA1002 is available in commercial (0 to +70 C) and extended (-40 to +85 C) temperature range, in a small 48 pins TQFP package.
index corner
48 1 2 3 4 5 6 7 8 9 10 11 12 13 DVCC
R
IPOL
VREFP VREFM
AGND
let o
Pr e
du o
N
(s) ct
O
Ob -
so
VIN
F
AGND VINB
eP let
14 15 DVCC DGND 16 CLK 17 DGND
ro
42
uc d
VCCB DR 41 40 39
N
38 37 NC 22 VCCB 23 OR 24 D9 (MSB)
TSA1002
s) t(
36 NC 35 NC 34 NC 33 D0 (LSB) 32 D1 31 D2 30 D3 29 D4 28 D5 27 D6 26 D7 25 D8
AGND
AVCC
AVCC
DFSB
NC
NC
O
TSA1002
AGND INCM
T
AGND AVCC AVCC
18 19 DGND NC
20 GNDB
21 GNDB
PACKAGE
7 x 7 mm TQFP48
APPLICATIONS Medical imaging and ultrasound Portable instrumentation Cable Modem Receivers High resolution fax and scanners High speed DSP interface
April 2004
1/20
TSA1002
ABSOLUTE MAXIMUM RATINGS
Analog Supply voltage 1) Digital Supply voltage
1) 1)
AVCC DVCC VCCB IDout Tstg ESD Latch-up
0 to 3.3 0 to 3.3 0 to 3.3
N
Max
Symbol
Parameter
Values
Unit V V V mA C KV KV
Digital buffer Supply voltage Digital output current Storage temperature Electrical Static Discharge - HBM - CDM-JEDEC Standard Class2)
E D W
Parameter
S E
Min 2.25 2.25 2.25
1) All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must never exceed -0.3V or VCC+0V
2) Corporate ST Microelectronics procedure number 0018695
OPERATING CONDITIONS
Symbol AVCC DVCC VCCB VREFP VREFM INCM Analog Supply voltage Digital Supply voltage
IG
2 1.5 A Typ 2.5
-100 to 100 +150
Forced top reference voltage 1)
R
Digital buffer Supply voltage
Forced bottom reference voltage1)
F
Forced input common mode voltage
1)Condition VRefP-VRefM>0.3V
BLOCK DIAGRAM
+2.5V
O
bs
let o
Pr e
VIN INCM VINB CLK
du o
Timing
N
(s) ct
stage 2
O
Ob -
so
te le
0.5 0
O
Pr
od
2.5 2.5 1 0 0.5
uc
N
2.7
s) t(
Unit V V V V V V
2.7
2.7 1.8 0.5 1.1
0.2
T
VREFP
GNDA stage n Reference circuit
stage 1
IPOL VREFM
Sequencer-phase shifting
DFSB OEB
Digital data correction
DR DO TO D9 OR
Buffers
GND
2/20
TSA1002
PIN CONNECTIONS (top view)
index corner
48 1 2 3 4 5 6 7 8
47 46
45
44 43
42
41 40
39
38 37 36 NC 35 NC 34 NC
IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM AGND AVCC AVCC
D
TSA1002
W
9 10 11 12 13 DVCC 14 15 DVCC DGND
E E
16 17 18 19 DGND 20 GNDB 21 GNDB 22 VCCB 23 24 OR D9 (MSB)
33 D0 (LSB) 32 D1 31 D2 30 D3 29 D4 28 D5 27 D6 26 D7 25 D8
S
ro P uc d s) t(
Description Observation CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) 2.5V 0V 2.5V 2.5V compatible CMOS input 2.5V compatible CMOS input 2.5V 2.5V 0V
R
N
O
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 7 8 9 Name IPOL VREFP VREFM AGND VIN
Description
Observation
Pin No
Analog bias current input Top voltage reference Bottom voltage reference 1V 0V 0V 1Vpp
Analog ground Analog input Analog ground Inverted analog input Analog ground
AGND VINB
AGND INCM AGND AVCC AVCC DVCC DVCC
Input common mode Analog ground
10 11 12 13 14
Analog power supply Analog power supply Digital power supply Digital power supply Digital ground Clock input Digital ground Non connected Digital ground Digital buffer ground Digital buffer ground
O
bs
16 17 18 19 20 21 22 23 24
15
let o
DGND CLK DGND NC DGND GNDB GNDB VCCB OR D9(MSB)
Pr e
od
ct u
0V 1Vpp 0V 0.5V 0V 2.5V 2.5V 2.5V 2.5V 0V
N
(s)
O
Ob 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
25
so
Name D8 D7 D6 D5 D4 D3 D2 D1
F
te le
Digital output
Digital output Digital output Digital output Digital output Digital output Digital output Digital output Least Significant Bit output Non connected Non connected Non connected Non connected Data Ready output Digital Buffer power supply Digital Buffer ground Digital Buffer power supply Non connected Non connected Output Enable input Data Format Select input Analog power supply Analog power supply Analog ground
T
D0(LSB) NC NC NC NC DR VCCB GNDB VCCB NC NC OEB DFSB AVCC AVCC AGND
2.5V compatible CMOS input 0V
0V 0V 0V 2.5V CMOS output (2.5V) CMOS output (2.5V)
43 44 45 46 47 48
Digital buffer power supply Out Of Range output Most Significant Bit output
IG
3/20
N
NC DR
AGND
AVCC
VCCB
GNDB
AVCC
DFSB CLK DGND
VCCB
OEB NC
NC
NC
TSA1002
ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V Tamb = 25 C (unless otherwise specified) TIMING CHARACTERISTICS
Symbol FS DC TC1 TC2 Tod Tpd Ton Toff Parameter Sampling Frequency Clock Duty Cycle Clock pulse width (high) Clock pulse width (low) Test conditions
Min 0.5 40 9 9
IG
Typ 50 10 10 5 5.5 1 1
N
Max 50 60 Unit Msps % ns ns ns cycles
Data Output Delay (Fall of Clock 10pF load capacitance to Data Valid) Data Pipeline delay Falling edge of OEB to digital output valid data Rising edge of OEB to digital output tri-state
W
D
E
S E N R
N+3 N+2 N+1
TIMING DIAGRAM
T
N-1 N
CLK
OEB
DATA OUT
bs O
let o
Tod
Pr e
N-7
du o
N-6
N
(s) ct
N-4
O
so Ob Tpd + Tod Toff
F
eP let
N+6
od r
N+7
uc
s) t(
ns
ns
O
N+8
Ton N-1 N+1 N+2
N-5
N-3
N-2
DR
HZ state
4/20
TSA1002
CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V Tamb = 25 C (unless otherwise specified)
Symbol
Parameter
Test conditions
Min
IG
Typ 2.0 13 5.0 1000 60 Typ 1.03
ANALOG INPUTS
N
Max Unit Vpp
S E D
Vin@ Full scale, FS=50Msps
VIN-VINB Full scale reference voltage Req Cin BW ERB Equivalent input resistance Input capacitance Analog Input Bandwidth Effective Resolution Bandwidth 1)
k
pF MHz MHz
1) See parameters definition for more information
REFERENCE VOLTAGE
Symbol VREFP Parameter Top internal reference voltage
W
E
Test conditions
Min 0.91
1)
Max
Tmin= -40 C to Tmax= 85 C
0.88 1.20
Vpol Ipol Ipol VINCM
Analog bias voltage Analog bias current
R
Tmin= -40 C to Tmax= 85 C1) Normal operating mode Shutdown mode
Analog bias current
Input common mode voltage
Tmin= -40 C to Tmax= 85 C1)
1) Not fully tested over the temperature range. Guaranteed by sampling.
bs O
let o
Pr e
du o
N
(s) ct
O
so Ob -
F
eP let
1.18 50 0.47 0.46
od r
1.27 70 0 0.57
uc
N
1.14
1.16
s) t(
Unit V V
1.35 1.36 100
V V A A
O
0.68 0.66
V V
T
5/20
TSA1002
CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V Tamb = 25 C (unless otherwise specified) POWER CONSUMPTION
Symbol ICCA Parameter
1)
Test conditions
Min
IG
Typ 15.6 1.3 2.5 40 48
N
18 21 2 2 5 5 60
Max
Unit mA mA mA mA mA mA A
Analog Supply current Tmin= -40 C to Tmax= 85 C2)
1)
1)
ICCB
Digital Buffer Supply Current Digital Buffer Supply Current in High Impedance Mode Power consumption in normal operation mode Power consumption in High Impedance mode
ICCBZ
1)
W
Tmin= -40 C to Tmax= 85 C2)
D
ICCD
Digital Supply Current
Tmin= -40 C to Tmax= 85 C2)
E
S
Min 2.0 2.4 -1.5 Min -40 -0.7 -0.8
100
1)
N
Pd
Tmin= -40 C to Tmax= 85 C2)
PdZ Rthja
1)
1) Rpol= 18K. Equivalent load: Rload= 470 and Cload= 6pF 2) Not fully tested over the temperature range. Guaranteed by sampling.
O
Junction-ambient thermal resistor (TQFP48)
DIGITAL INPUTS AND OUTPUTS
Symbol
Parameter
Digital inputs VIL Logic "0" voltage
VIH
Logic "1" voltage
Digital Outputs VOL VOH IOZ
Logic "0" voltage
O
ACCURACY
Symbol OE DNL INL 6/20 Parameter Offset Error Differential Non Linearity Integral Non Linearity Monotonicity and no missing codes Test conditions
Fin= 2MHz, VIN@+1dBFS Fin= 2MHz, VIN@+1dBFS Fin= 2MHz, VIN@+1dBFS
bs
CL
let o
Logic "1" voltage
High Impedance leakage current OEB set to VIH Output Load Capacitance
ro P e
du
N
(s) ct
O
so Ob Test conditions
T
F
Pr te le
R
od
43 80
uc
62
s) t(
E
mW mW
48
mW C/W
Typ
Max
Unit
0.8
V V
Iol=10A Ioh=-10A
0.4
V V
1.5 15
A pF
Typ -2 0.2 0.3
Max 40 +0.7 +0.8
Unit mV LSB LSB
Guaranteed
TSA1002
CONDITIONS AVCC = DVCC = 2.5V, Fs= 40Msps Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V Tamb = 25 C (unless otherwise specified) DYNAMIC CHARACTERISTICS
Symbol Parameter Test conditions Fin= 5MHz Fin= 10MHz Fin= 24MHz SFDR Spurious Free Dynamic Range Fin= 5MHz Fin= 10MHz Fin= 24MHz Fin= 5MHz
2) 1)
Min
IG
Typ -79.2 -77 -69 59.5 59.4 59.0
N
Max -65.5 -68.5 -63.4 -61.5 -62.8 -58.5 dBc dBc Unit dB -77.8 -76 -68.1
D
58.5 58.3 57.4 57.9
SNR
Signal to Noise Ratio
Fin= 5MHz
E
Fin= 10MHz Fin= 24MHz
W
1)
E
2)
S
57.1 55.9
N
Fin= 10MHz Fin= 24MHz Fin= 5MHz
R
THD
Total Harmonic Distortion Fin= 5MHz Fin= 10MHz Fin= 24MHz Fin= 5MHz
2)
O
Fin= 10MHz Fin= 24MHz
1)
SINAD
Signal to Noise and Distortion Ratio
ENOB
bs O
let o
Effective Number of Bits Fin= 5MHz Fin= 10MHz Fin= 24MHz
2)
Pr e
du o
N
ct
(s)
O
Fin= 10MHz Fin= 24MHz
Ob 1) 2) 1)
so
F
eP let
58.5 58.2 57.0 57.8 56.9 55.3 9.6 9.5 9.3 9.4 9.3 9
od r
59.4 59.3 58.5
uc
s) t(
dB
-63.5 -67.4 -62.5 -62.3 -60.7 -57.6 dB dB
T
dB
Fin= 5MHz Fin= 10MHz Fin= 24MHz Fin= 5MHz Fin= 10MHz Fin= 24MHz
dB
9.76 9.71 9.60 bits
bits
1) Rpol= 18K. Equivalent load: Rload= 470 and Cload= 6pF 2) Tmin= -40 C to Tmax= 85 C. Not fully tested over the temperature range. Guaranteed by sampling.
7/20
TSA1002
DEFINITIONS OF SPECIFIED PARAMETERS STATIC PARAMETERS Static measurements are performed through method of histograms on a 2MHz input signal, sampled at 40Msps, which is high enough to fully characterize the test frequency response. The input level is +1dBFS to saturate the signal. Differential Non Linearity (DNL) The average deviation of any output code width from the ideal code width of 1 LSB. Integral Non linearity (INL) An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. DYNAMIC PARAMETERS Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB.
N
Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 x ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD2Ao=SINADFull Scale+ 20 log (2A0/FS) SINAD2Ao=6.02 x ENOB + 1.76 dB + 20 log (2A0/ FS) The ENOB is expressed in bits.
W
D
E
S
Signal to Noise and Distortion Ratio (SINAD)
IG
E
Dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies and sampled at 40Msps.
R
Analog Input Bandwidth
The input level is -1dBFS to measure the linear behavior of the converter. All the parameters are given without correction for the full scale amplitude performance except the calculated ENOB parameter.
Spurious Free Dynamic Range (SFDR)
N
The ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in dBc. Total Harmonic Distortion (THD)
The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB.
bs O
let o
Pr e
du o
(s) ct
O
so Ob -
The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels.
F
te le
O
ro P
uc d
Effective Resolution Bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. Also called data latency. It is expressed as a number of clock cycles.
8/20
T
N
s) t(
TSA1002
Static parameter: Integral Non Linearity Fs=50MSPS; Fin=1MHz; Icc=20mA; N=131072pts
0 .8 0 .6 0 .4
INL (LSBs)
0 .2 0 - 0 .2 - 0 .4 - 0 .6 - 0 .8
O u tp u t C o d e
W
0
200
400
D
600 800
E
1000
S N
Fs=50MSPS; Fin=1MHz; Icc=20mA;N=131072pts
0 200
IG
Dynamic parameters (dB)
Static parameter: Differential Non Linearity
0 .5 0 .3
E
R
0 .4 0 .2 0 .1 0 -0 .1 -0 .2 -0 .3 -0 .4 -0 .5
DNL (LSBs)
Linearity vs. Fs Fin=5MHz; Rpol adjustment
100
Dynamic parameters (dB)
ENOB (bits)
bs O
90 80 70
let o
od Pr e
ENOB SNR SINAD
ct u
N
(s)
O
400
so Ob -
T
F
te le
O
ro P
uc d
600
800
O u tp u t C o d e
Distortion vs. Fs Fin=5MHz; Rpol adjustment
10 9 8 7 6 5 4
-30 -40 -50 -60 -70 -80 -90 -100 -110 -120 25 35 45 55 SFDR THD
60 50 40 30 25 35 45 55
Fs (MHz)
Fs (MHz)
N
s) t(
1000
9/20
TSA1002
Linearity vs. Fs Fin=15MHz; Rpol adjustment
100 10
Dynamic parameters (dB)
Dynamic parameters (dB)
90 80 70
ENOB
-40 -50 -60 -70 -80 -90 -100 -110 -120 THD
9 ENOB (bits) 8
SNR 60 SINAD 50 40 30 25 35 45 55
7 6 5 4
D
25 35 45
E
S
SFDR 55
W
Fs (MHz)
IG
Fs (MHz)
-30
N
Linearity vs. Fin Fs=50MSPS; Icca=20mA
80
E
Distortion vs. Fin Fs=50MSPS; Icca=20mA
-30
10
Dynamic parameters (dB)
75 ENOB 70 65 60 55 50
9.5 9
Dynamic parameters (dB)
-40 -50 -60 -70 -80 -90
8 7.5 7 6.5
ENOB (bits)
8.5
SNR
SINAD
45 40
T
6
0
20
40
Fin (MHz)
Linearity vs.Temperature Fs=50MSPS; Icca=20mA; Fin=5MHz
bs O
65 60 55 50 45
Dynamic Parameters (dB)
70
Dynamic Parameters (dB)
let o
od Pr e
ENOB SNR
ct u
60
N
(s)
5
5.5
O
so Ob -100 0
F
te le
O
ro P
THD
R
uc d
SFDR
20
40
N
s) t(
60
Distortion vs. Fs Fin=15MHz; Rpol adjustment
Fin (MHz)
Distortion vs. Temperature Fs=50MSPS; Icca=20mA; Fin=5MHz;
10 9.8 9.6 9.4 9.2 9 8.8 8.6 8.4 8.2 8
90 85 80 75 70 65 60 55 50 45 -40 10 60 THD SFDR
SINAD
-40
10
60
Temperature ( C)
Temperature ( C)
10/20
TSA1002
Linearity vs. AVcc Fs=50MSPS; Icca=20mA; Fin=1MHz
64 10
-50
Dynamic Parameters (dB)
Dynamic parameters (dB)
63 62 61 60 59 58 57 56 2.25 SNR SINAD ENOB
9.9 9.8 9.7 9.6 9.5 9.4 9.3 9.2 9.1 9 2.35 2.45 2.55 2.65
-55 -60 -65 -70 -75 -80 -85 -90 -95
ENOB (bits)
S E
2.35
-100 2.25
D
2.45 2.55
IG
SFDR THD 2.65
AVCC (V)
W
AVCC (V)
N
Linearity vs. DVcc Fs=50MSPS; Icca=20mA; Fin=1MHz
64
E
Distortion vs. DVcc Fs=50MSPS; Icca=20mA; Fin=1MHz
-40
10 9.9 9.8 9.7 9.6 9.5
Dynamic parameters (dB)
62 60 58 56 54 52 50 2.25 SNR ENOB
Dynamic parameters (dB)
-50 -60 -70 -80 -90
ENOB (bits)
SINAD
2.35
2.45
2.55
2.65
DVCC (V)
Linearity vs. VccB Fs=50MSPS; Icca=20mA; Fin=1MHz
70
Dynamic parameters (dB)
64 62 60 58 56
ENOB
ENOB (bits)
bs O
66
68
9.9 9.8 9.7 9.6 9.5 SNR SINAD 9.4 9.3 9.2 9.1 9
Dynamic Parameters (dB)
let o
ro P e
uc d
N
(s) t
9.4 10
O
so Ob -
F
te le
2.35
O
ro P
SFDR THD
T
R
uc d
-100 2.25
2.45
N
s) t(
2.55 2.65 2.55 2.65
Distortion vs. AVcc Fs=50MSPS; Icca=20mA; Fin=1MHz
DVCC (V)
Distortion vs. VccB Fs=50MSPS; Icca=20mA; Fin=1MHz
-40 -50 -60 -70 -80 -90 -100 2.25 THD SFDR
54 2.25
2.35
2.45
2.55
2.65
2.35
2.45
VCCB (V)
VCCB (V)
11/20
DETAILED INFORMATION The TSA1002 is a high speed analog to digital converter based on a pipeline architecture and the latest deep submicron CMOS process to achieve the best performances in terms of linearity and power consumption. The pipeline structure consists of 9 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. Each 8 first stages consists of an Analog to Digital converter, a Digital to Analog converter, a Sample and Hold and a gain of 2 amplifier. A 1.5bit conversion resolution is achieved in each stage. The latest stage simply is a comparator. Each resulting LSB-MSB couple is then time shifted to recover from the conversion delay. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB)
R
couple for each stage. The corrected data are outputted through the digital buffers. Input signal is sampled on the rising edge of the clock while digital outputs are delivered on the falling edge of the Data Ready signal. The advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. The highest dynamic performances are achieved while consumption remains at the lowest level. Some functionalities have been added in order to simplify as much as possible the application board. These operational modes are described in the following table. The TSA1002 is pin to pin compatible with the 8bits/40Msps TSA0801, the 10bits/25Msps TSA1001 and the 12bits/50Msps TSA1201. This ensures a conformity within the product family and above all, an easy upgrade of the application.
W
D
E
DR
CLK CLK CLK CLK CLK CLK HZ
S
IG
Outputs
E
OPERATIONAL MODES DESCRIPTION
Inputs DFSB
Analog input differential level
(VIN-VINB) -RANGE RANGE> (VIN-VINB) -RANGE RANGE> > > (VIN-VINB) > > (VIN-VINB) X RANGE (VIN-VINB) >-RANGE RANGE (VIN-VINB) >-RANGE
Data Format Select (DFSB)
bs O
When set to low level (VIL), the digital input DFSB provides a twois complement digital output MSB. This can be of interest when performing some further signal processing. When set to high level (VIH), DFSB provides a standard binary output coding. Output Enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state. This results in lower consumption while the converter goes on sampling.
let o
Pr e
du o
N
(s) ct
H H H L L L X
O
Ob OEB
L L L L L L H
so
OR
H H L H H L HZ
F
te le
O
ro P
uc d
N
Most Significant Bit (MSB)
D9 D9 D9 Complemented D9 Complemented D9 Complemented D9 HZ
T
When OEB is set to low level again, the data is then valid on the output with a very short Ton delay. The timing diagram page 4 summarizes this operating cycle. Out of Range (OR) This function is implemented on the output stage in order to set up an "Out of Range" flag whenever the digital data is over the full scale range. Typically, there is a detection of all the data being at i0i or all the data being at i1i. This ends up with an output signal OR which is in low level state (VOL) when the data stay within the range, or in high level state (VOH) when the data are out of the range.
12/20
N
TSA1002 APPLICATION NOTE
s) t(
TSA1002
Data Ready (DR) The Data Ready output is an image of the clock being synchronized on the output data (D0 to D9). This is a very helpful signal that simplifies the synchronization of the measurement equipment or the controlling DSP. As digital output, DR goes in high impedance state when OEB is asserted to High level as described in the timing diagram page 4. REFERENCES AND COMMON MODE CONNECTION VREFM must be always connected externally. Internal reference and common mode The VREFP, VREFM voltages set the analog dynamic at the input of the converter that has a full scale amplitude of 2*(VREFP-VREFM). In case of analog dynamic lower than 2Vpp, the best linearity and distortion performance is achieved while increasing the VREFM voltage instead of lowering the VREFP one. The INCM is the mid voltage of the analog input signal. It is possible to use an external reference voltage device for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. Using the STMicroelectronics TS821 or TS4041-1.2 Vref leads to optimum performances when configured as shown on Figure 2. Figure 2 : External reference setting
O
In the default configuration, the ADC operates with its own reference and common mode voltages generated by its internal bandgap. VREFM pin is connected externally to the Analog Ground while VREFP (respectively INCM) is set to its internal voltage of 1.03V (respectively 0.57V). It is recommended to decouple the VREFP in order to minimize low and high frequency noise (refer to Figure 1)
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1k
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TS821 TS4041 external reference
E
VCCA VREFP VIN
1.03V
F
Figure 1 : Internal reference and common mode setting
330pF 10nF 4.7uF
TSA1002
VINB VREFM
VIN
VREFP 0.57V
330pF 10nF
O
TSA1002
VINB INCM VREFM
External reference and common mode Each of the voltages VREFM, VREFP and INCM can be fixed externally to better fit to the application needs (Refer to Table iOPERATING CONDITIONSi p2 for min and max values).
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Pr e
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(s) ct
4.7uF
so Ob -
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R
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330pF 10nF 4.7uF
T
At 15Msps sampling frequency, 1MHz input frequency and -1dBFS amplitude signal, performances can be improved up to 2dB on SFDR and 0.3dB on SINAD. At 50Msps sampling frequency, 1MHz input frequency and -1dBFS amplitude signal, performances can be improved up to 1dBc on SFDR and 0.6dB on SINAD. This can be very helpful for example for multichannel application to keep a good matching among the sampling frequency range.
13/20
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TSA1002
DRIVING THE ANALOG INPUT Differential inputs The TSA1002 has been designed to obtain optimum performances when being differentially driven. An RF transformer is a good way to achieve such performances. Figure 3 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. Figure 3 : Differential input configuration with transformer
Analog source ADT1-1 1:1 VIN
50 100pF
Figure 5 : DC-coupled 2Vpp differential analog input
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D
analog
E
DC DC
Figure 5 shows a DC-coupled configuration with forced INCM to the DC analog input (mid-voltage) while VREFM is connected to ground and VREFP is let internal (1V); we achieve a 2Vpp differential amplitude.
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AC+DC
Figure 4 represents the biasing of a differential input signal in AC-coupled differential input configuration. Both inputs VIN and VINB are centered around the common mode voltage, that can be let internal or fixed externally.
N
VIN VINB
VREFP
E
TSA1002
VINB INCM
TSA1002
N
analog
330pF
10nF
4.7uF
R
VREFP-VREFM = 1 V
The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.57V. The INCM is decoupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from Minicircuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. For example, with internal references, each analog input can drive a 1Vpp amplitude input signal, so the resultant differential amplitude is 2Vpp.
Figure 4 : AC-coupled differential input
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50 50
Pr e
100k
du o
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(s) ct
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so Ob -
F
Single-ended input configuration The single-ended input configuration of the TSA1002 requires particular biasing and driving. The structure being fully differential, care has to be taken in order to properly bias the inputs in single ended mode. Figure 6 summarizes the link from the differential configuration to the single-ended one; a wrong configuration is also presented. - With differential driving, both inputs are centered around the INCM voltage. - The transition to single-ended configuration implies to connect the unused input (VINB for instance) to the DC component of the single input (Vin) and also to the input common mode in order to be well balanced. The mid-code is achieved at the crossing between VIN and VINB, therefore inputs are conveniently biased. - Unlikely other structures of converters in which the unused input can be grounded; in our case it will end with unbalanced inputs and saturation of the internal amplifiers leading to a non respect of the output codes.
eP let
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INCM
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VREFM 4.7uF
330pF
10nF
T
10nF 33pF 10nF
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VIN INCM
100k
TSA1002
common mode
VINB
14/20
TSA1002
Figure 6 : Input dynamic range for the various configurations
+FS: code 1023 VIN - VINB +FS: code 1023 VIN - VINB VINB VIN INCM VIN 0: code 511 0: code 511 VINB INCM
+FS + offset: code > 1023
-FS: code 0
D
-FS + offset: code > 0 VIN VINB Ao + ac
Ao + ac
W
-FS: code 0 Ao + ac VIN VINB
VIN
E
VINB INCM Ao
S
INCM
IG
VIN
Ao + ac
INCM Ao
E
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The applications requiring single-ended inputs can be configured like reported on Figure 7 for an AC-coupled input or on Figure 8 and 9 for a DC-coupled input.
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Figure 8 : DC-coupled 2Vpp analog input
Analog
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In the case of AC-coupled analog input, the analog inputs Vin and Vinb are biased to the same voltage that is the common mode voltage of the circuit (INCM). The INCM and reference voltages may remain at their internal level but can also be fixed externally.
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Figure 7 : AC-coupled Single-ended input
Signal source
50 common mode 33pF
10nF
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let o
Pr e
100k 100k
du o
VIN INCM VINB
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so Ob Analog
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AC+DC
Ao Wrong configuration!
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VIN VINB
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T
330pF
VREFP-VREFM = 1 V
Figure 9 : DC-coupled 1Vpp analog input
AC+DC DC VIN
TSA1002
In the case of DC-coupled analog input with 1V DC signal, the DC component of the analog input set the common mode voltage. As an example figure 8, INCM is set to the 1V DC analog input while VREFM is connected to ground and VREFP let internal; we achieve a 2Vpp differential amplitude. Figure 9 describes a configuration for a 1Vpp analog signal with a 0.5V DC input. In this case, while VREFP is kept internally at 1V, VREFM is connected to VINB and INCM externally to 0.5V; the dynamic is then 1Vpp (VREFP-VREFM=0.5V).
0.5V power supply
330pF
VREFP-VREFM = 0.5 V
Dynamic characteristics, while not being as remarkable as for differential configuration, are still of very good quality. Measurements done at 50Msps, 2MHz input frequency, -1dBFS input level sum up these performances. An SFDR of -64.5dBc, a SNR of 57.8dB and an ENOB Full Scale of 9.3bits are achieved.
15/20
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INCM INCM
10nF
Differential configuration
Single-ended configuration: balanced inputs
Single-ended configuration: unbalanced inputs
VIN - VINB
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VREFP
TSA1002
VREFM
4.7uF
TSA1002
VINB VREFM INCM
10nF
4.7uF
TSA1002
Power consumption The internal architecture of the TSA1002 enables to optimize the power consumption according to the sampling frequency of the application. For this purpose, a resistor is placed between IPOL and the analog Ground pins. The figure 10 sums up the relevant data. The TSA1002 will combine highest performances and lowest consumption at 50Msps when Rpol is in the range of 12k to 20k. At lower sampling frequency, this value of resistor may be changed and the consumption will decrease as well. Figure 10 : Analog Current consumption vs. Fs According value of Rpol polarization resistance
60 50 RPOL 20 18 16 14 12 10 8
Distortion vs. Duty cycle Fs=50MSPS; consumption optimized; Fin=1MHz
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Dynamic Parameters (dB)
-40 -50 -60 -70 -80 -90 -100 -110 -120
IG S E
30 40 50 ENOB THD SFDR IccA 60 70
-30
70 60 IccA (mA) ENOB (bits)
60
50 40 30 20 10
W
D
Duty Cycle (%)
30
Rpol (kOhms)
Icca (mA)
N
40
Linearity vs. Duty cycle Fs=50MSPS; Icca=20mA; Fin=10MHz
80
R
20 ICCA 10 0 25 35 45
Dynamic parameters (dB)
6 4 2 0
75 70 65 60
55
65
75
Fs (MHz)
T
Linearity, distortion performance towards Clock Duty Cycle variation
The TSA1002 has an outstanding behaviour towards clock duty cycle variation and it may be also reinforced with adjustment of analog current consumption. Linearity vs. Duty cycle Fs=50MSPS; consumption optimized; Fin=1MHz
80
Dynamic parameters (dB), analog current cons. (mA)
50 40 30 20 10 0 30 40 IccA
SINAD
ENOB (bits)
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bs
ENOB SNR
Dynamic Parameters (dB)
70 60
let o
Pr e
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ct
(s)
10 9 8 7 6 5 4 3
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Ob -
so
55 50 45 40 35 30 40
F
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45
O
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10 9.5 9 8.5 8 7.5 7 6.5 6 5.5 5
E
SNR
SINAD
50
55
60
Duty Cycle (%)
Distortion vs. Duty cycle Fs=50MSPS; Icca=20mA; Fin=10MHz
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 40 45 50 55 SFDR THD
50
60
70
Duty Cycle (%)
Duty Cycle (%)
16/20
TSA1002
Clock input The quality of your converter is very dependant on your clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator is recommended. The clock power supplies must be separated from the ADC output ones to avoid digital noise modulation at the output. It is recommended to keep the circuit clocked, to avoid random states, before applying the supply voltages. Layout precautions To use the ADC circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: - Proper termination of all inputs and outputs is needed; with output termination resistors, the amplifier load will be only resistive and the stability of the amplifier will be improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. - To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output capacitance, buffers or latches close to the output pins will relax this constraint. - Choose component sizes as small as possible (SMD). EVAL1002 evaluation board
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- First of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is recommended for high speed circuit applications to provide low inductance and low resistance common return.
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The characterization of the board has been made with a fully ADC devoted test bench as shown on Figure 11. The analog signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the 74LCX573 octal buffers. All characterization measurement has been made with an input amplitude of +0.2dB for static parameters and -0.5dB for dynamic parameters.
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- Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion.
F
The separation of the analog signal from the digital part is essential to prevent noise from coupling onto the input signal.
Figure 11 : Analog to Digital Converter characterization bench
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HP8644
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Data ADC evaluation board Clk HP8133 Pulse Generator Logic Analyzer Clk PC
Sine Wave Generator
HP8644
Sine Wave Generator
17/20
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TSA1002
s) t(
12
1BCCV 01 42C Fn074 91C Fn01 81J 74 53C 4J BMS/JLC
+
1BccV
12
2NOC 61J 74 63C
12
01
+
CCVD 51J
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1BdnG 2 1 22J 32C Fn074 22C Fn01
ro P
2BdnG 2 1 12J 05 3R
Fp033
33C Fn01 04C Fn074 83C 375XCL47 EL DNG 7Q 7D 6Q 6D 5Q 5D 4Q 4D 3Q 3D 2Q 3U 2D 1Q 1D 0Q 0D CCV BEO 01 9 8 7 6 5 4 3 2 1 375XCL47 EL DNG 7Q 7D 6Q 6D 5Q 5D 4Q 2U 4D 3Q 3D 2Q 2D 1Q 1D 0Q 0D CCV BEO
3 81C Fp033 TW1-1TA-2T 1T
71C F01
1
12C Fp033 02C
DNGD 2 1 02J
21D 11D 01D 9D 8D 7D 6D 5D 4D 3D 2D 1D OD RD 62C Fn01 11 21 31 41 51 61 71 81 91 02 11 21 31 41 51 61 71 81 91 02
222221111111 432109876543
52 62 72 82 92 03 13 23 33 43 53 63 21D 1 R 3 11D 01D 9D 8D 7D 6D 5D 4D 3D 2D 1D D
D O 5. N N G N G C G V V 2GGDCD LDDD V CDDN NKNC C BB CUUD D DC C B UFF FFF F
so Ob -
Figure 12: TSA1002 Evaluation board schematic
(s) ct
Fp033
6J
73C 74
+
1BCCV 82C
CCVA 61C K74 31R K74
21R K74 11R K74
2BCCV
21
71J V3FFUBDDV
21
21
21
21
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11J
01J BEO
9J BSFD
let o
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Pr e
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93C Fn074
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01 9 8 7 6 5 4 3 2 1
1U
2 52 V. G 5. CNV CBC C AAA BD B G ODVVN E FCC DRUUUNN BB CCD FFF 0 F F FCC S
2001AST CDA stib41-8
CCVA CCVA DNGA MCNI DNGA BNIV DNGA niV DNGA MferV PferV lopI
21 11 01 9 8 7 6 5 4 3 2 1
Fp033 2C
Fn01 Fn074 4C 3C
CCVA
Fp033
Fn01 Fn074
5C
6C
7C
Fp033
Fn01 Fn074
8C
9C
01C
Fp033
333444444444 789012345678
K74 K74 K74 K74 K74 K74 91R 81R 71R 61R 51R 41R Fp033 52C Fn01 72C Fn074
11C
Fn01 Fn074 Fp033 03C 21C 31C
Fn01 13C
Fn074 23C
Fp001 1C
TW1-1TA-2T 4
2
6
2T
Fp033
41C Fn01
K1 2R
51C Fn074
K74 1jaR
+
E
W
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23 13 03 92 82 72 62 52 42 32 22 12 02 91 81 71 61 51 41 31 21 11 01 9 8 7 6 5 4 3 2 1 RO 31D
te le
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+
NIP23
4
92C
2
6
F01 14C
F74 24C
DNGA 2 1 91J
CCVA 1 2 21J edoM moc seM 2 1 8J edom moc lgeR 2 1 7J
3 05 1R
1
1J niV
MferV 2 1 5J
PferV 2 1 2J
18/20
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TSA1002
Figure 13: Printed circuit of evaluation board
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Printed circuit board - List of components
P art D e sign F o o t print at o r 1210 1210 1210 1210 P a rt T ype D esign F o o tprint at o r T ype 10 uF 10 uF 10 uF 10 uF 10 0pF 10 nF 10 nF C24 C23 C41 C29 C1 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 4 7uF 4 7uF 4 7uF 4 7uF 4 70 nF 4 70 nF 4 70 nF 4 70 nF 4 70 nF 4 70 nF 4 70 nF
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10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 1K 3 2P IN 3 30pF 3 30pF
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let o
C 12 C39 C 15 C40 C27 C4 C21 C31 C6 C9 C 18 R2 J6 C25 C26
E
ro P e
60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 ID C 32 60 3 60 3
du
C 33 C 20 C8 C2 C5 C 11 C 30 C 17 C 14 C 36 C 34 C 35 C 42 C 22 C 32 C 37 C 38 C 13 C 28 C 10
N
(s) ct
60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 CAP CAP CAP CAP 80 5 80 5 80 5 80 5 80 5 80 5 80 5
O
so Ob P a rt T ype 470 nF 470 nF 470 nF 470 nF 47K 47K 47K 47K 47K 47K 47K 47K 47K 47K 47K 50 50 a to r C7 C 16 C 19 C3 R 12 R 14 R 11 R aj1 R 10 R 19 R 13 R 15 R 16 R 17 R 18 R3 R1
T
F
te le
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R
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D es ign F o o t print
P art T ype
D es ign at o r J12 J4 J19 J9 J2 0 J15 J2 2 J2 1
8 05 8 05 8 05 8 05 6 03 6 03 6 03 VR5 6 03 6 03 6 03 6 03 6 03 6 03 6 03 6 03 6 03 T S S O P 20 T S S O P 20 S IP 2
A VC C C LJ / S M B A GN D D F SB D GN D D VC C G ndB 1 G ndB 2
M e s c o m mo de J8 OEB J10
R egl co m m o de J7 T 2- A T 1- 1WT T 2- A T 1- 1WT V cc B 1 V D D B UF F 3V V in V ref M V ref P T S A 100 2 T2 T1 J18 J17 J1 J5 J2 U1
74LC X 57 3 U3 74LC X 57 3 U2 CON 2 J 16
19/20
N
s) t(
F o o t print F IC H E 2M M SM B / H F IC H E 2M M F IC H E 2M M F IC H E 2M M F IC H E 2M M F IC H E 2M M F IC H E 2M M F IC H E 2M M F IC H E 2M M F IC H E 2M M AD T AD T F IC H E 2M M F IC H E 2M M SM B / H F IC H E 2M M F IC H E 2M M T Q F P 48
TSA1002
PACKAGE MECHANICAL DATA 48 PINS - PLASTIC PACKAGE
48 1
e
37 36
E
E3 E1 E
W
12 13 24
25
D
c
B
S
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Inches Typ. Max.
0.063 0.006 0.057 0.011 0.008 0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039 0.030 20/20
0,10 mm .004 inch SEATING PLANE
N
D3 D1 D
E
L1
L
R
K
0,25 mm .010 inch GAGE PLANE
Millimeters Typ.
F
Dim.
A A1 A2 B C D D1 D3 e E E1 E3 L L1 K
Min.
0.05 1.35 0.17 0.09
bs O
let o
Pr e
du o
N
(s) ct
9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00
O
1.40 0.22
so Ob Max.
1.60 0.15 1.45 0.27 0.20
te le
Min.
0.002 0.053 0.007 0.004
T
O
0.45
0.75
0.018
0 (min.), 7 (max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States (c) http://www.st.com
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A1
A A2
N

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